Digital electronic systems, such as computers, have long required random access memory systems for relatively quick access to data. Over time, and with the increasing complexity of electronic systems, such memory systems have developed into implementations using a memory controller providing a memory interface to a memory bus to which one or more memory devices are coupled.
Digital electronic systems have continued to become ever faster, and the speeds at which such memory interfaces operate have continued to increase. Furthermore, the timing windows used in such memory interfaces, i.e., the periods of time during which a signal in such a memory interface is deemed to be stable enough to be reliably latched have continued to be shortened as part of this speeding up such memory interfaces.
Reliable latching of a signal requires that a signal have propagated the length of a conductor from the component transmitting the signal to the component receiving the signal, and the passage of enough additional time to compensate for effects on the signal from any imperfections in the conductor or variations from the design characteristics of either the transmitting or receiving components. In other words, due to a number of factors that could affect the quality or the precision of the timing of a signal, it has long been common practice to “pad” the timing by which a signal is latched to ensure that a signal that has been received is fully “settled” (i.e., stable) at the time that latching occurs. In earlier systems with slower interfaces, timing windows were often lengthy enough to provide both considerably more time to allow a signal to stabilize before latching, and a considerable amount of time after the latching of a signal before transmission of the signal by a transmitting component would end. However, current systems with faster interfaces cannot afford to provide such lengthy timing windows, because each transfer of signals is provided with less time in which to take place.
It is common practice to mount memory devices used in such a memory system to one or more circuit boards with conductive traces forming a memory bus to connect such memory devices to the memory interface provided by a memory controller. It is often the case that traces connecting one memory device to a memory controller are of a different length than traces connecting another memory device to the same memory controller. It is also common practice to design the logic of memory controllers to use the same timing in latching corresponding signals received from multiple memory devices in such a system.
However, mismatches in trace lengths between different memory devices and a memory controller can cause the timing window for the latching of one signal from one memory device by a memory controller to be shifted in time relative to the timing window during for the latching of a corresponding signal from another memory device by the same memory controller. In other words, even if two substantially identical memory devices with substantially identical timing characteristics transmit corresponding signals at the same time, the fact that the signal sent by one memory device must propagate across a longer trace than the corresponding signal of the other memory device will cause the timing window for the signal sent by the one memory device to both start and end later than the timing window for the signal sent by the other memory device at the point where those signals reach the memory controller.
For a memory controller to use the same timing with corresponding signals from different memory devices where the timing windows are shifted relative to each other, the timing used by the memory controller must be set to cause latching to occur during a time in which the shifted timing windows overlap. However, as timing windows have continued to be shortened as part of speeding up memory interfaces, the amount of time during which such shifted timing windows overlap has continued to decrease, leaving progressively less time for stability of signals to be achieved and held so that latching may reliably take place.